FE Design Implementation Engineer

Summary Posted: Dec 7, 2022 Role Number:200350818 Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you will help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You will ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you will be crafting and building the technology that fuels Apple’s devices. Together, we enable our customers to do all the things they love with their devices. In this role, you will be responsible for synthesis, timing closure, and power optimisation of Apple developed GPUs. As part of the Hardware design team, you will collaborate closely with the RTL Design and PD teams to ensure creation of the highest quality gate-level netlists. Key Qualifications

• Experience with front-end design synthesis and large chip integration;
• Proficient in timing analysis, formal logic equivalence and lint checks;
• Proficient in multi-clock, multi-mode and multi-power-domain designs;
• Understanding of physical concepts like floor-planning, placement, congestion, and setup/hold timing closure;
• Hands on experience with ECOs for functionality and timing;
• Ability to propose logically equivalent RTL transforms to reduce power & area;
• Familiarity with DFT insertion;
• Familiarity with simulation, debugging tools and experience of working closely with design verification team;
• Scripting and programming experience;
• Experience with RTL - System Verilog or VHDL;
• Experience working on CPUs, GPUs, or DSPs is desirable;
• Excellent written and verbal communication, excellent organisation skills, and highly self-motivated;
• Ability to work well in a team and be productive under aggressive schedules.

Description Own unit RTL to gate-level netlist synthesis Use advanced synthesis techniques to meet aggressive timing, power, and area targets Propose novel synthesis and RTL solutions to improve netlist quality Work with RTL design and Physical Design teams to deliver best-in-class GPU designs Education & Experience MS in EE/CS/ECS Additional Requirements